library ieee;

use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.cpu_utils.all;



entity reg is
	generic (
		size : integer := 32;
		Tpd : Time := unit_delay
	);
	port (
		clock: in bit;
		clear : in bit;
		load : in bit;
		d : in bit_vector(size-1 downto 0);
		q : out bit_vector(size-1 downto 0)
	);
end reg;


architecture reg_arh of reg is
begin
	process(clock, clear, load, d)
	begin
		if(clock'event and clock='1')then
				if clear = '1' then q <= (q'range=>'0') after Tpd;
				elsif load = '1' then q <= d after Tpd;
				end if;
		end if;
	end process;
end reg_arh;